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In electronics and computing, the flip-flop or bistable multivibrator is an electronic circuit which in its simplest form consists of two transistors (or vacuum tubes) connected in such a way that the circuit can be in one of two stable conditions. A trigger applied at an appropriate point can cause the circuit to flip from one state to the other. A trigger at another point can cause the circuit to flop back to the other state. It is also possible to arrange it so that repeated triggers at one point cause it to change state back and forth.

The first electronic flip-flop was invented in 1919 by W. H. Eccles and F. W. Jordan. It was initially called the Eccles-Jordan trigger circuit.

## Types of flip-flops

### T flip-flop

One way of changing the state is to have the flip-flop's state invert when a
clock signal changes state. Usually they change only when the clock moves in a particular direction, e.g. low (ground) to high (for example 5 volts). This is called a T-type (for "toggle") flip-flop. Several T flip-flops can be connected together to form a divide by N counter.

Characteristic equation:

### S-R flip-flop

Another type of flip-flop changes when a set or clear input is pulsed. This is called an S-R (for "set/reset") flip-flop.

### J-K flip-flop

A third type of flip-flop is composed of a pair of S-R flip-flops connected in series as a Master and Slave. The Master section receives the inputs and is gated by a clock while the Slave section is gated by an inversion of that clock. The Slave's outputs are cross-coupled back to the input gates of the Master as well as being the outputs. This is called an J-K flip-flop. By connecting its J and K inputs in various different ways this versatile flip-flop could be configured to toggle, store data, and perform many other functions.

A J-K flip-flop operates as follows:

• If both inputs are logic 0, the flip-flop remains in the same state as it was before the clock pulse occurred.
• If both inputs are logic 1, the flip-flop changes state whenever the edge of a clock pulse occurs (T flip-flop behaviour).
• If one input (J or K) is at logic 0, and the other is at logic 1, then the output is set or reset (by J and K respectively).

Characteristic equation:

### D flip-flop

A fourth type records an input's state (the data) when a clock is pulsed. This is called a D-type (for "data") flip-flop.

Left: A circuit symbol for a D-type flip-flop, where > is the clock input, D is the data input and Q is the stored data output.

Characteristic equation: Qnext = D

## Use

The flip-flop can be used to store one bit, or binary digit, of data. The data may represent the state of a sequencer, the value of a counter, an ASCII character in a computer's memory or any other piece of information.

One use is to build finite state machines from electronic logic. The flip-flops remember the machine's previous state, and digital logic uses that state to calculate the next state.

The "T" flip-flop is useful for counting. Repeated signals to the clock input will cause the flip-flop to change state once per high-to-low transition of the clock input. The output from one flip-flop can be fed to the input of a second and so on. The final output of the circuit, considered as the array of outputs of all the individual flip-flops, is a count, in binary, of the number of cycles of the first clock input, up to a maximum of 2n-1, where n is the number of flip-flops used.

One of the problems with such a counter is that the output is briefly invalid as the changes ripple through the logic. To solve this problem, there are circuits called "synchronous counters". These use more logic to assure that the outputs of the counter all change at the same, predictable time.

Frequency division: a chain of "T" flip-flops as described above will also function to divide an input in frequency by 2n, where n is the number of flip-flops used between the input and the output.

Registers to store numbers in computers. A "D" flip-flop can represent one digit of a binary number. The computer's control unit puts out the clock signal at the right time to capture the data.

## Timing and Metastability

Clocked flip-flops are prone to a problem called metastability, which happens when a data or control input is changing at the instant of the clock pulse. The result is that the output may behave unpredictably, taking many times longer than normal to settle to its correct state, or even oscillating several times before settling. In a computer system this can cause corruption of data or a program crash.

In many cases, metastability in flip-flops can be avoided by ensuring that the data and control inputs are held constant for specified periods before and after the clock pulse, called the setup time (tsu) and the hold time (th) respectively. These times are specified in the data sheet for the device, and are typically between a few nanoseconds and a few hundred nanoseconds for modern devices.

Unfortunately, it is not always possible to meet the setup and hold criteria, because the flip-flop may be connected to a real-time signal that could change at any time, outside the control of the designer. In this case, the best the designer can do is to reduce the probability of error to a certain level, depending on the required reliability of the circuit. One technique for suppressing metastability is to connect two or more flip-flops in a chain, so that the output of each one feeds the data input of the next, and all devices share a common clock. With this method, the probability of a metastable event can be reduced to a negligible value, but never to zero.

So-called metastable-hardened flip-flops are available, which work by reducing the setup and hold times as much as possible, but even these cannot eliminate the problem entirely. This is because metastability is more than simply a matter of circuit design. When the transitions in the clock and the data are close together in time, the flip-flop is forced to decide which event happened first. However fast we make the device, there is always the possibility that the input events will be so close together that it cannot detect which one happened first. It is therefore logically impossible to build a perfectly metastable-proof flip-flop.

Another important timing value for a flip-flop is the propagation delay (common symbol in data sheets: tprop). It is the time the flip-flop takes before its output changes after the clock edge. The propagation delay may be different for the high-to-low and the low-to-high transitions. Data sheet symbols are tPHL and tPLH respectively.  