PA-RISC is a microprocessor architecture developed by Hewlett-Packard's Systems & VLSI Technology Operation. As the name implies, it is an implementation using a RISC design, where the PA stands for Precision Architecture. The design is also referred to as HP/PA for Hewlett Packard Precision Architecture.
In the late 1980s HP was building two series of computers, both on CISC CPUs. One was the HP-9000 Unix workstations, designs based on the Motorola 68000 family they had acquired when they purchased Apollo. The other was the HP-3000 series minicomputers, based on an HP designed 16-bit CPU. HP was looking to use the PA-RISC to move all of their machines to a single RISC CPU family.
The first PA-RISC 7000 family were 32-bit designs, and were first used in a new series of HP-3000 machines in the late 1980s, the 930 and 950. They were commonly known at the time as Spectrum systems, the name given to them in the development labs. The HP-9000 machines were soon upgraded with the PA-RISC as well, running the HP/UX version of UNIX (although other operating systems, such as Linux and MPE/iX (the HP-3000's OS) can be used).
An interesting aspect of the PA-RISC line is that most of its generations have no Level 2 cache. Instead large Level 1 caches are used, at formerly as separate chips connected by a bus, now integrated on-chip. Only the PA-7100LC, PA-7200, and PA-7300LC had L2 caches. Another innovation of the PA-RISC was the addition of multimedia instructions (SIMD) in the form of MAX which were first introduced on the 7100.
The design was upgraded in 1996 to the PA-RISC 2.0 architecture, which is fully 64-bit, with the PA-8000's release. It featured no fewer than ten functional units and an aggressive pipelining system. Another change was the splitting of the instruction cache, with separate caches for instructions that take long or short time to complete. The PA-8200 was released in 1997 and was much like the PA-8000 with better branch prediction, lower TLB miss rates, and larger, faster caches.
The PA-8500 design added the cache to the main chip, with no less than 1.5MB of Level 1 cache. Consequently, it was a great performer for its time. The 8600 is essentially a higher clocked 8500 with a few architectural improvements. The 8700 is clocked higher than the 8600, to which it is similar, and has 2.25 MB of L1 cache. It is worth noting that the relatively high latencies of the integrated L1, a tradeoff due to its size, probably limit performance. However, for it's time, the large integrated cache was impressive.
The PA 8800, codenamed Mako, will feature 2 independent microprocessors on a single die. Thus each "chip" will be a 2-way SMP set. Each processor on the Mako has a 1.5 MB L1 cache, but HP is breaking with its L1-only design custom by including 32 MB of L2 cache using separate chips. The processor will be packaged in a "cartridge" format like the Pentium II and is expected to perform well. After the PA-8900, an improved Mako, HP is expected to retire the PA-RISC line in favor of the Itanium line. The core design introduced with the PA-8000 has not changed significantly to date; each later generation has concentrated only on increasing clock speed and integrating incremental improvements like larger caches and, finally, 2 cores on one chip. Along with the MIPS architecture, the PA-RISC is in something just a bit above "maintenance mode" as a commercial UNIX-machine CPU.
